In fabrication of semiconductor integrated circuits, efforts to decrease the size of MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor) consisting semiconductor integrated circuits have been continued to obtain highly integrated semiconductor elements having excellent performance.
As a result of such efforts, the art for fabrication of semiconductor integrated circuits has scaled down to reach to sub-micron level.
Scale down of a semiconductor element has to be carried out in horizontal direction as well as in vertical direction proportional to the horizontal direction to balance with various characteristics of other elements.
That is, when an element is to be scaled down, for example distance between a source and a drain is to come closer, not wanted characteristic changes of an element is to cause, of which the short channel effect is typical.
To solve the short channel effect, a horizontal dimension(length of a gate) as well as a vertical dimension(thickness of a gate insulation film, joining depth etc.,) have to be decreased, and accordingly the applied voltage has to be lowered, the doping concentration of the substrate has to be thickened, and especially, the doping profile of channel area has to be adjusted.
However, despite an element in an electronic product has to meet the required applied voltage of the product, because the applied voltage required for electronic products using semiconductor elements has not been decreased though the dimension of semiconductors has been decreasing, in case of semiconductor elements, particularly NMOS transistors have become to have a weak structure against hot carrier developed by accelerated electrons applied to a source accelerated by an abrupt high electric field near a drain due to a short channel effect developed by the decreased distance between the source and the drain.
According to a reference paper [Chenming Hu et al., "Hot Electron-Induced MOFET Degradation Model, Monitor and Improvement," IEEE Transactions on Electron Devices, Vol. ED-32, No.2, 1985, pp.375 to 385], the instability by hot carrier is due to by a very high electric field caused by a short channel length and an high applied voltage near a drain junction. Consequently, a LDD structure having improved the structure of existing NMOS which is weak against hot carrier with a short channel length was proposed.
The feature of a LDD structure disclosed in a paper [K. Saito et al., "A New Short Channel MOSFET with Lightly Doped Drain," Denshi Tsushin Rengo Taikai 1978, pp 220] is one that solved the instability of elements due to hot carrier by designing a N-area(low density impurity area) formed to have a narrow width and self-aligned to spread-out the high electric field near the drain junction so that carriers(electrons)applied from the source are not to be accelerated even in a high electric field.
In developing a technology for fabrication of elements having an integration over 1M DRAM, many a technology for fabrication of MOSFETs having LDD structure are proposed, in which a LDD forming method using a gate side wall spacer is typical, that has been being used in most mass-production technology until now.
The LDD forming method using a gate side wall spacer is to be explained hereinafter, referring to FIGS. 1.
First, as shown in FIG. 1(a), a gate oxide film 3, a conduction layer 4 for forming gate poles and a gate cap oxide film 5 are formed successively on a P type semiconductor substrate 5 an active area on which a transistor will be formed with a field oxide film 2 has been defined thereon.
Then, as shown in FIG. 1(b), a gate pole is formed by carrying out a patterning of the cap oxide film 5 and the conduction layer 4 using a gate pole pattern.
Next, as shown in FIG. 1(c), a N-area 6 is formed for the gate pole 4 in a self-aligning way on the substrate by ion injecting phosphor(p) in low density as a N type impurity.
Then, as shown in FIG. 1(d), an oxide film 7 is formed over the substrate with CVD(Chemical Vapor Deposition) method, and, as shown in FIG. 1(e), the CVD oxide film 7 is etched back with RIE(Reactive Ion Etching) technique to form gate side wall spacers.
Next, as shown in FIG. 1(f), a N+source and a drain area 8 are formed having a deeper junction depth by a high density ion injection of N type impurity. In this time, because the gate side wall spacer serves as a mask in the high density ion injection process for forming the N+source and the drain areas, it is possible to form a N-area 6 between the gate channel and the N+source and the drain areas.
However, a method for fabrication of transistors having a LDD structure utilizing the gate side wall spacer described above has a few problems, particularly above method is not appropriate for an practicable technology for fabrication of next generation semiconductor elements requiring high integration and high quality.
That is, because the additional process of the gate side wall spacer forming process features that carrying out etch back after deposition of a CVD Oxide film, the silicon substrate of the active area become exposed in the etch back process, the active area exposed thus, is overetched (ie., damage to the silicon substrate), of which overetched depth shows a serious non-uniformity of different aspect between them depending on the position of silicon substrate and the density of patterns, therefore non-uniform electric characteristic of an element is exhibited depending on the position of a chip.
Further, the plasma radical species of CF4, CHF3 and O2 etc., used in the etch back process for side wall spacer forming infiltrate into the silicon substrate, though it depends on RF power in the etching process, forming chemical compound layers of CFx-Polymer, Si--C bond, Si--O bond, Si--O--C bond etc., within a range of 500 Angstroms from the surface of the silicon substrate.
FIG. 2 shows a SIMS(secondary ion mass spectroscopy) analyzed profile of a silicon substrate after etching of an oxide film, wherein the CFx-polymer, Si--C bond, Si--O bond and Si--O--C bond can be seen. Therefore, in high integration elements requiring shallow junction, because the bonding sites of the chemical compounds described above exist within a depletion region under the voltage applied to junctions serving as trap centers developing carriers resulting to cause the leakage current of the junction to increase. This is explained in detail in the paper of [Jae Jeong Kim et al.," Cleaning process for removing oxide etch residue," Proceeding of contamination control and defect reduction in semiconductor manufacturing I, pp. 408 to 415, 1992, Toronto]"
Another problem in LDD structure forming method using gate side wall spacer is that, because the gate side wall spacer is generally formed almost vertical to the silicon substrate, making stress to concentrate on the edge area where the gate space meets with the substrate, dislocation lines are formed from the edge of the side wall spacer to the direction of bulk of the substrate as shown in FIG. 3 depending on the shape of the gate side wall spacer.
That is, as shown in FIG. 4, depending on the angle to the silicon substrate, the stress on the silicon substrate is of the ranges of 2.7 10 dyn/cm(FIG. 4(b) to 5.4 10 dyn/cm(FIG. 4(a)), which stress concentrate on the edge region where the side wall spacer and the silicon substrate meet, and the more steeper the slope of the gate side wall spacer, the easier the development of the dislocation. As shown in FIG. 5, an increase of the dislocation causes an increase of the junction leakage current of an element. and consequently causes element fail. This is described in detail in the paper of [Shigeo Onishi et al., "Formation of a Defect Free Junction later by controlling defects due to As+ Implantation," IEEE/IRPS, 1991, pp. 255 to 259].
Following the decrease of element size, the tolerance of fabrication process has been decreased, which makes the deterioration of element characteristic (particularly, increase of junction leakage current) caused by the overetch of the silicon substrate developed in the processes of CVD oxide film deposition and etching, which is the core process of the gate side wall spacer forming method, the plasma radical species infiltration, and the dislocation due to the side wall spacer profile, become a great problem.
Accordingly, researches for solving problems described above in another method other than the conventional method utilizing side wall spacer is in progress.
As a representative method, there is a method disclosed in the paper [Shigeo Onishi et al., "Formation of Defect free Junction later by controlling defects due to As+ Implantation," IEEE/IRPS, 1991, pp. 255 to 259], which is to be explained hereinafter, referring to FIG. 6.
After forming up to a low density impurity area (N-area) by the same process with the fabrication process for transistors of LDD structure described above, as shown in FIG. 6(a), as an etch prevention layer 9 which can protect the silicon substrate on the etch back of the CVD oxide film, a nitride film etc., are formed over a substrate a gate pole 4 having been formed thereon, and as shown in FIG. 6(b), a CVD oxide film is etched back after forming on the etch prevention layer 9 to form gate side wall spacers 10 and high density ion injection is carried out to form high density N+source and drain areas 8 as shown in FIG. 6(c). That is, it is a technology preventing pollution of the substrate due to the plasma radical species of the etchant in the etch back process of the CVD oxide film by an etch prevention layer.
However, even the method described above can not solve the problem of development of dislocations caused by the side wall spacers perfectly.